In a receiver, the equalizer (EQ) and the clock data recovery circuit (CDR) are essential blocks in order to demodulate the attenuation digital signal to the correct information.
The equalizer commonly is the discrete equalizer (DEQ) by using a linear equalizer (LEQ) plus a level of post-cursor. One of the most widely used discrete equalizers is the decision feedback equalizer (DFE).
The clock data recovery circuit can be implemented by many means, which can be roughly classified as analog clock data recovery circuits and digital clock data recovery circuits. The analog clock data recovery circuit can integrate the clock phase error information to provide a control voltage of the voltage controlled oscillator to calibrate the phase. The digital clock data recovery circuit transfers the clock phase error information into phase shift digital code by logical circuits, and then calibrates the phase by the phase interpolator (PI).
However, the bottleneck of the current technology is the arrangement order of the equalizer and the clock data recovery circuit. If the clock data recovery circuit is arranged ahead the discrete equalizer, the equalization effect of the linear equalizer needs to be large enough to allow the clock data recovery circuit to operate properly. The drawbacks are that the noise will be enlarged simultaneously and the power consumption will be increased. Nevertheless, if the clock data recovery circuit is arranged behind the discrete equalizer, the edge value of signal will be determined by the sampling clock of the equalizer. Therefore, it is necessary to use the signal before the equalizer incorporating more logical operation to calibrate it, so that the complexity and area of the circuit are highly increased.
Therefore, the best mean is to combine the clock data recovery circuit and the discrete equalizer, so as to conduct equalization and calibration simultaneously. However, all of the current innovations of combining the clock data recovery circuit and the discrete equalizer use the discrete equalizer and Hogge phase detecting device, but this phase detecting device is only applicable to the analog clock data recovery circuit.
FIG. 1A depicts the circuit diagram of Alexander phase detecting device 1 of the prior art. FIG. 1B depicts a timing chart of the phase detecting device 1 in FIG. 1A of the prior art. The phase detecting device 1 comprises three D-type flip-flops (Da, Db, and Dc), a first XOR gate (Xor1), and a second XOR gate (Xor2).
The D-type flip-flop (Da) obtains the first sample data (D1) of the input data signal (DataIn) in light of the positive clock signal (Clki) and generates the first serial data, for example, the odd serial data (Odd). The D-type flip-flop (Db) obtains the second sample data (D2) of the input data signal (DataIn) in light of the negative clock signal (Clki) and generates the second serial data, for example, the even serial data (Even). The D-type flip-flop (Dc) obtains the transition data (T1) of the input data signal (DataIn) in light of the edge clock signal (Clkq) and generates the transition data (Edge).
The first XOR gate (Xor1) executes an XOR operation for the first sample data (D1) of the first serial data (Odd) and the transition data (T1) of the transition data (Edge) to obtain the first clock phase shift information (UP). The second XOR gate (Xor2) executes the XOR operation for the second serial data (Even) and the transition data (T1) of the transition data (Edge) to obtain the second clock phase shift information (DN). The first clock phase shift information (UP) and the second clock phase shift information (DN) are utilized to adjust the phases of these clock signals (Clki), (Clki), and (Clkq), so as to make them simultaneously lead forward or lag backward.
However, the aforementioned phase detecting device 1 can obtain the first clock phase shift information (UP) and the second clock phase shift information (DN) only, but does not have the function of feedback equalization. Therefore, the phase detecting device 1 is not able to conduct equalization and calibration for the input data signal (DataIn) simultaneously.
Consequently, how to overcome the above problems of the prior art, in fact, has become anxious to resolve the issue.